Department of Computer Science
The University of Chicago

Last modified: Tue Feb 2 18:52:01 CST 1999

The project work for Com Sci 222/322 is being designed. It will probably be similar to a subset of the Bucknell project. You will use the VeriLog Hardware Definition Language, and the VeriWell simulator, to explore some aspects of computer design, probably a simple pipeline.

• Project #1, due Wednesday 10 February.
• Project #2, due Friday 19 February. Solution
• Project #3, due Friday, 5 March. Solution
• Project #4, due Friday, 12 March

odonnell@cs.uchicago.edu