Department of Computer Science
The University of Chicago

Last modified: Tue Feb 8 12:50:02 CST 1999

Project 1, practice with VeriWell

Due Wednesday, 10 February, midnight

Please get started on this project assignment right away.

Start with my VeriLog program for a Counter Machine.

1. Speed up the clock as much as you can without introducing errors. Don't change any code affecting the operation of the machine, except for the two parameter statements defining the clock speed. You should change the program initialization, however to make the clearest possible test of correctness.
2. Although only a bit more than half of the executions of the ``Instruction fetch'' section actually fetch an instruction from memory, the 3-step control must leave enough time for a memory delay in all cases. Speed up the machine further by generating a signal as soon as the IR is known to be loaded properly, instead of waiting a fixed amount of time. You may also change the clock speed again. Be careful not to change any of the instruction execution logic, nor any of the assumed delays.

Although the amount of programming in this project step is quite small, there is a lot of room to get confused. Please start promptly, and start asking questions.

odonnell@cs.uchicago.edu