Department of Computer Science
The University of Chicago

Last modified: Thu Feb 25 21:49:10 CST 1999

Project step #3, computer
Due Friday, 5 March, midnight

In step 3 of the project you implement a simple computer, using Verilog HDL at the behavioral level.

Use the basic structure of the simple counter machine provided in Project 1. In particular, keep the 3 instruction execution steps (fetch, increment PC, execute).

Project step tasks

1. Expand the width of memory words and general registers to 16 bits.



2. Expand the memory to 256 words. Keep the delay of 50 time steps for each memory access.



3. Expand the PC register and the IR register width to deal with the longer addresses needed for a memory of 256 words.



4. Modify the instruction set to a simple Load/Store architecture. The fixed-length instruction formats are shown in Table 1 below, and the operation codes are defined in Table 2. Every memory access (instruction fetch, load, store) takes 50 time steps. Every access to a register, and every control operation that tests values in registers (including PC and IR), takes 1 time step. Using your experience from Project 2 imagine a 16 bit ALU (similar to the one in Project 2 but on 16 bits and built using these gates that all have a delay of 1). Determine the maximum ALU delay from your new ALU, and apply it to all ALU operations. The delays shown in Table 2 are only for the instruction execution step: you must apply appropriate delays to the other steps.



5. Test your new computer. Use tiny simple tests to make sure that each instruction behaves as specified, and that control passes appropriately from one instruction to the next.



6. Demonstrate your new computer: Write and run a program that calculates the gcd (greatest common divisor) of two positive numbers. Assume that the two numbers are in M[0] and M[1] before your program starts. When your program terminates, the gcd value must be in M[2]. Also, when your program terminates it should display the memory values M[0], M[1] and M[3]. Keep all intermediate values in registers. You are not responsible for the behavior of the program on nonpositive inputs. Use the following version of Euclid's algorithm to compute the gcd:

   
   while (b > 0) {
   
      c = b;
   
      if (a < b) then b = a else b = a - b;
   
      a = c;
   
   }
   

   Compile the algorithm by hand into the most straightforward machine code. Don't do any clever programming.

   Run your program on at least the following inputs: (128, 36) and (55, 21)

7. Extra credit: Create the ALU you imagined in step 4 and incorporate it into you CPU to execute the ADD, SUB, INC, DEC operations, instead of specifying them at the behavioral level. Test and demonstrate your computer again with the ALU.



8. Without adding new control signals reduce as much as you can the clock period (if this is possible).



9. Test and demonstrate your computer again.

Materials to hand in

Hand in:

matei@cs.uchicago.edu