Com Sci 222/322
Computer Architecture
Winter 1999

Design Project Step #2

Department of Computer Science

The University of Chicago

Last modified: Fri Feb 12 11:38:17 CST 1999

Project step #2, Simple ALU
Due Friday, 19 February, midnight

Submission instructions

Although you don't need to write a lot of code, there's a lot of potential for confusion, so please start looking over the project and asking questions right away.

In Project step #1 you played with the architecture of a toy computer with only four instructions. What you wrote was mainly a behavioral model in Verilog HDL. This means you specified what but not how the Verilog HDL code is to be realized (synthesized, in the jargon) in digital circuits. For example, you wrote:

       #1      PC = PC + 1;

as part of the increment PC stage. This specifies that the contents of PC register is to be incremented but not how this is to be accomplished. Here you will specify, at gate level, how increment (and other simple aritmnetic and logical operations) are to be performed. This is called structural modeling in Verilog HDL.

Project step goals

In Project step #2, you will implement an 8-bit ALU according to the following specifications:


input:          a[7:0]          - first operand
                b[7:0]          - second operand
                OpCode[1:0]     - operation code

output:         Result[7:0]     - the result
                Overflow        - overflow
                
operations that your ALU should support and their opcodes:
                ADD (00)         result <- a + b
                SUB (01)         result <- a - b
                INC (10)         result <- a + 1
                DEC (11)         result <- a - 1

integer representation: 2's complement

technique: ripple carry adder

Use the design from Computer Organization & Design, Chapter 4.

Project step resources

Implement all logic in project step #2, with the AND, OR, NOT, and MUX_2 modules provided in gates.v. These modules have appropriate delays built in.

Project step tasks

Define a 1-bit half-adder module called half_adder_1. A half adder takes 2 wires, a and b, as input, and produces result and CarryOut output wires.

Combine 2 1-bit half adders to define a 1-bit complementing full-adder module called adder_1, with a, b, CarryIn, and Binvert input wires, Result and CarryOut output wires, as shown in Figure 4.16 of CO&D.

Combine 8 1-bit full adders into an 8-bit adder_8 module called adder_8. Provide a[7:0], b[7:0], Binvert, and CarryIn input wires, and provide Result[7:0] and Overlow output wires.

Define an ALU_8 module containing a single instance of your adder_8 module. Instead of CarryIn and Binvert input wires, provide OpCode[1:0] input wires.

Com Sci 322 only: Improve the speed of the adder through carry lookahead. That is, implement 2 4-bit ripple adders, and combine them with a carry-lookahead unit into an 8-bit adder (see Figure 4.24).

Test each step before going on to the next. For the final ALU_8_control module, demonstrate the range of latency in additions. Define all test inputs in separate test modules. For each task t (1-5), create separate test files with names of the form test_t-n.v, so that the test may be executed by running

veriwell test_t-n.v

The set of tests should be sufficient to create strong confidence in the correctness of your program, and should demonstrate the latency.

Materials to hand in

Hand in:

readme file (please write your name and email address at the top)

source code - both for ALU module(s) and test module

test results

Maintained by Matei Ripeanu, email:

matei@cs.uchicago.edu

Com Sci 222/322 Computer Architecture Winter 1999