| Name | Action |
|---|
| Load | Store | ALU | Branch |
|---|
| 1 | Instruction Fetch (IF) |
IR <- Mem[PC]
NPC <- PC + 4
|
| 2 | Instruction decode/register fetch (ID) |
A <- Regs[IR6..10]
B <- Regs[IR11..15]
Imm <- sign-extend(IR16..31)
|
| 3 | Execution/effective address (EX) |
ALUOut <- A + Imm
|
ALUOut <- A op B
or
ALUOut <- A op Imm
|
ALUOut <- NPC + Imm
Cond <- (A op 0)
|
| 4 | Memory access/branch completion (MEM) |
LMD <- Mem[ALUOut]
|
Mem[ALUOut] <- B
|
idle |
if (cond)
PC <- ALUOut
else
PC <- NPC
|
| 5 | Write-back (WB) |
Regs[IR11..15] <- LMD
|
idle |
Regs[IR16..20] <- ALUOut
or
Regs[IR11..15] <- ALUOut
|
idle |